1. Field of the Invention
The present invention relates to comparator based switch capacitor circuit, in particular to comparator based switch capacitor circuit that performs circuit error averaging.
2. Description of Related Art
Comparator based switch capacitor (CBSC) circuit is an emerging technology that offers many advantages over conventional operational amplifier based switch capacitor circuit. Like a conventional switch capacitor circuit, a CBSC circuit also works in a two-phase manner. The two phases are “sampling” phase and “transfer’ phase, controlled by two non-overlapping clocks, say φ1 and φ2, respectively. In a typical two-phase CBSC circuit working at a sampling rate off, the duration of each phase is slightly less than half of the sampling clock period T=1/f During sampling phase (φ1), an input voltage VI is sampled using a sampling capacitor C1 by connecting the “+” end of C1 to VI and the “−” end to a common mode voltage VCM. During transfer phase (φ2), the charge stored on the sampling capacitor C1 is transferred to an integrating capacitor C2 via a charge transfer circuit comprising a comparator 130 and a charge pump (CP) 140, which includes a current source I1 and a current sink I2, as shown in FIG. 1. In FIG. 2, CL is a load capacitor for the CBSC circuit 100, VDD is a supply voltage, VSS is the lowest potential in the system. Note that VCM is the common mode voltage that is usually close to the mean value of VDD and VSS. Also, CL is terminated to VCM via a sampling switch 150, which is controlled by a switch signal S. The purpose of the charge transfer circuit is to transfer the charge stored on C1 to C2 until the potentials on its two ends are equal, i.e. VX=VCM. The principle of the CBSC circuit 100 during transfer phase (φ2) is briefly described as follows.
At the beginning of the charge transfer phase, a brief preset (P) must be performed to clear CL and ensure the voltage VX is below VCM. The preset is done by momentarily pulling the output node VO to VSS, the lowest potential in the system. Next, a coarse charge transfer phase (E1) begins. During coarse charge transfer phase, VX<VCM and CP 140 turns on the current source I1 to inject charge into the circuit comprising CL, C2, and C1, resulting in a relatively fast voltage ramp on VX toward VCM. CP 140 continues to inject charge until comparator 130 detects VX>VCM. At the instant where comparator 130 detects VX>VCM, a fine charge transfer phase (E2) commences by turning off the current source I1 and turning on the current sink I2 to drain charge from the circuit comprising CL, C1, and C2. One deliberately chooses I2 to be lower than I1 resulting in a relatively slow voltage ramp down on VX back toward VCM. At the instant where the comparator 130 detects VX<VCM again, the sampling switch 150 is opened and the charge stored on CL is sampled and frozen.
FIG. 2 depicts a typical timing diagram for the CBSC circuit 100 for the charge transfer phase. Initially the switch signal S is asserted. As a result, the sampling switch 150 is closed and the load CL is terminated to VCM. In the mean while, VO stays at the sampled level from the previous cycle and VX is close to VCM. The transfer phase φ2, starting at time t1 and ending at time t5, comprises four sub-phases: preset (P), coarse charge transfer (E1), fine charge transfer (E2), and hold (H). The CBSC circuit 100 first enters the P phase (at time t1), where it pulls the output node VO to VSS and causes VX to drop to VXO, which is below VCM. At time t2, it enters the E1 phase, where comparator detects VX<VCM and CP 140 injects charge into the circuit comprising CL, C2, and C1, resulting in relatively fast voltage ramp up on both VO and VX. The E2 phase starts at time t3, the instant where comparator 130 detects VX>VCM. Note that due to circuit delay, t3 slightly trails the exact time instant where VX rises past VCM. During the E2 phase, CP 140 drains charge from the circuit comprising CL, C2, and C1, resulting in a relatively slow voltage ramp down on both VO and VX. Finally, the CBSC circuit 100 enters the H phase at time t4, where comparator 130 detects VX<VCM again. Again, due to circuit delay, t4 slightly trails the exact time instant where VX falls past VCM. During the H phase, S is de-asserted and thus the charge stored on CL is frozen, and also charge pump circuit CP 140 is disabled.
There are two problems associated with the prior art CBSC circuit 100. First, there is always an error on the final sampled value of VO due to the circuit delay. As clearly seen in FIG. 2, the actual sampled value is always slightly lower than the ideal sample value, which is the value at the exact time instant where VX falls past VCM. Second, the prior art CBSC circuit 100 is subject to error due to the offset in the comparator 130.
What is needed is a method to remove the errors due to circuit non-idealities, in particular circuit delay and comparator offset, for CBSC circuit.